The invention relates to an MRAM memory in which the drive logic arrangement for driving the magnetoresistive memory components in a memory cell array of the MRAM memory is integrated below the memory cell array in and on the semiconductor substrate.
MRAM memory components have ferromagnetic layers, the resistance of the memory component depending on the magnetization directions of the ferromagnetic layers. The resistance of the memory component is small in the case of parallel magnetization of the ferromagnetic layers, whereas the resistance of the memory component is large in the case of an antiparallel magnetization of the ferromagnetic layers.
Depending on the construction of the layer structure of the MRAM component, a distinction is made between a GMR memory component, a TMR memory component, an AMR memory component and a CMR memory component.
A GMR memory component has at least two ferromagnetic layers and a nonmagnetic conductive layer arranged in between, the GMR memory component exhibiting a xe2x80x9cGMR effectxe2x80x9d (GMR: Giant Magneto Resistance), in the case of which the electrical resistance of the GMR memory component depends on whether the magnetizations in the two ferromagnetic layers are oriented in a parallel or antiparallel manner.
A TMR memory component (TMR: Tunneling Magneto Resistance) has at least two ferromagnetic layers and an insulating nonmagnetic layer arranged in between. In this case, the insulating layer is made so thin that a tunneling current occurs between the two ferromagnetic layers. The ferromagnetic layers exhibit a magnetoresistive effect brought about by a spin-polarized tunneling current through the insulating nonmagnetic layer arranged between the two ferromagnetic layers. The electrical resistance of the TMR memory component depends on whether the magnetizations of the two ferromagnetic layers are oriented in a parallel or antiparallel manner.
In the case of the AMR memory component, the resistance of the magnetized conductors is different parallel and perpendicular to the magnetization direction.
In the case of the CMR memory component (CMR=Colossal Magneto Resistance Effect), high coercive forces mean that a high magnetic field is required for changing over between the magnetization states.
FIG. 1 shows a memory cell array of an MRAM memory according to the prior art (e.g. DE 197 44 095), which comprises a multiplicity of metallic write/read lines, also called word and bit lines, which are arranged one above the other in the x- and y-direction, and magnetoresistive memory components which are each connected between two mutually crossing write/read lines and are conductively connected thereto. Signals which are applied to the word lines WL or bit line BL cause magnetic fields as a result of the currents flowing through the word lines WL or bit lines BL, respectively, which magnetic fields, given sufficient strength, influence the memory components situated underneath. In order to write a datum or an information item to a memory component situated at a crossover point between a word line WL and a bit line BL, a signal is applied both to the bit line BL and to the word line WL. The current signals each generate magnetic fields which are superposed and lead to magnetization reversal of the memory component. The mutually crossing word lines WL and bit lines can each be produced with minimal dimensions and distances with a minimal feature size F, resulting in an area requirement of 4F2 for each memory component per memory cell layer. MRAM memories can therefore be produced with a very high packing density.
Compared with DRAM memories, these MRAM memories are distinguished by the fact that the individual memory components do not require a selection transistor, but rather are connected directly to the word and bit lines. The memory cell array illustrated in FIG. 1 has just one memory cell layer. In MRAM memories, a plurality of such memory cell layers can be arranged or stacked one above the other. The dimensions of the memory components of the conventional MRAM memories are in a range from 0.05 xcexcm to 20 xcexcm. On account of the small size of the memory components, which do not require a selection transistor, and on account of the high possible packing density and also on account of the possible multilayer construction, in MRAM memories a multiplicity of memory components can be integrated within a very small space. The magnetoresistive memory components situated in the memory cell array are driven via a drive logic arrangement.
FIG. 2 shows the construction of an MRAM memory according to the prior art. The memory cell array comprising the magnetoresistive memory components is connected via a contact-making fan-out to the drive logic arrangement, which is arranged around the memory cell array. In the conventional MRAM memory illustrated in FIG. 2, the drive logic arrangement is situated in the periphery of the semiconductor chip and bears on the semiconductor substrate. The drive logic arrangement is connected to the word and bit lines. As can be discerned from FIG. 3, the peripherally arranged drive logic arrangement takes up a large area on the semiconductor substrate. Although the memory cell array constructed from magnetoresistive memory components takes up relatively little space, the conventional MRAM memory illustrated in FIG. 2 overall requires a relatively large area on the semiconductor substrate on account of the peripherally arranged drive logic arrangement.
The object of the present invention, therefore, is to provide an MRAM memory which has a minimal area requirement.
This object is achieved according to the invention by means of an MRAM memory having the features specified in patent claim 1.
The invention provides an MRAM memory having a memory cell array comprising magnetoresistive memory components arranged in at least one memory cell layer above a semiconductor substrate, having word lines and bit lines for making contact with the magnetoresistive memory components in the memory cell array, and having a drive logic arrangement for driving the magnetoresistive memory components in the memory cell array via the word and bit lines, the drive logic arrangement being integrated below the memory cell array in the semiconductor substrate.
In this case, the word and bit lines preferably run essentially perpendicularly to one another.
In a preferred embodiment, the magnetoresistive memory components and the word and bit lines for making contact with the magnetoresistive memory components are embedded in a plurality of dielectric layers.
In this case, the word and bit lines are preferably connected via plated-through holes running through the dielectric layers to the drive logic arrangement integrated in the semiconductor substrate.
In a preferred embodiment, the diameter of the plated-through holes approximately corresponds to the minimum feature size F.
The drive logic arrangement is preferably a CMOS logic arrangement.
In a further preferred embodiment, a memory component in each case has two ferromagnetic layers and a nonmagnetic layer arranged in between.
A memory component of the MRAM memory preferably has two magnetization states.
In a particularly preferred embodiment, the two ferromagnetic layers of the memory component each contain at least one of the elements Fe, Ni, Co, Cr, Mn, Gd, Dy.
The thickness of the ferromagnetic layers of the memory component is preferably less than or equal to 20 nm.
In a further preferred embodiment of the MRAM memory according to the invention, the nonmagnetic layer contains at least one of the materials Al2O3, NiO, HfO2, TiO2, NbO and SiO2.
In this case, the thickness of the nonmagnetic layer is preferably in a range between 1 and 4 nm.
In a further preferred embodiment, the memory component has an antiferromagnetic layer which is adjacent to one of the ferromagnetic layers and determines the magnetization direction in the adjacent ferromagnetic layer.
In this case, the antiferromagnetic layer preferably contains at least one of the elements Fe, Mn, Ni, Pt, Ir, Tb or O.
In a further preferred embodiment, the dimensions of a memory component are in a range between 0.05 xcexcm and 20 xcexcm.
The bit lines are preferably connected to a sense amplifier, via which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off.
In this case, the sense amplifier preferably contains a feedback operational amplifier.
In a particularly preferred embodiment, the total thickness of a single-layer memory cell array with the underlying and overlying bit and word lines is between 400 and 1000 nm. Multilayer memory cell arrays with the associated write and read lines are correspondingly multiply thicker.
In a further preferred embodiment of the MRAM memory according to the invention, each word line is in each case connected to two magnetoresistive memory components in two memory cell layers lying one above the other.
This affords the particular advantage that the number of required word lines can be halved.
A preferred embodiment of the MRAM memory according to the invention is described below with reference to the accompanying figures in order to elucidate features that are essential to the invention.